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ESDALC5-1BM2, ESDALC5-1BT2
Single line low capacitance TransilTM for ESD protection
Features

Single line low capacitance Transil diode Bidirectional ESD protection Breakdown Voltage Vbr = 5 V min. Low diode capacitance (26 pF typ at 0 V) Low leakage current < 50 nA @ 3 V Very small PCB area: 0.6 mm
SOD882 ESDALC5-1BM2 SOD882T ESDALC5-1BT2
Benefits

High ESD protection level High integration Suitable for high density boards Lead-free "Halogen-free" according to ECOPACK(R)2
I/O1
Figure 1.
Functional diagram
Complies with the following standards:
IEC 61000-4-2 level 4 - 15 kV (air discharge) - 8 kV (contact discharge) MIL STD 883G - Method 3015-7: class 3 - Human body model
I/O2
Applications
Where transient overvoltage protection in ESD sensitive equipment is required, such as:

Description
The ESDALC5-1BM2 and ESDALC5-1BT2 are bidirectional single line TVS diodes designed to protect datalines or other I/O ports against ESD transients. These devices are ideal for applications where both reduced line capacitance and board space saving are required.
Computers Printers Communication systems Cellular phone handsets and accessories Video equipment
TM: Transil is a trademark of STMicroelectronics
February 2010
Doc ID 16936 Rev 1
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www.st.com 14
Characteristics
ESDALC5-1BM2, ESDALC5-1BT2
1
Characteristics
Table 1.
Symbol VPP PPP
(1)
Absolute maximum ratings (Tamb = 25 C)
Parameter Peak pulse voltage IEC 61000-4-2 contact discharge Tj initial = Tamb Value 30 150 9 - 55 to + 150 - 65 to + 150 260 Unit kV W A C C C
Peak pulse power dissipation (8/20 s) Peak pulse current (8/20 s) Junction temperature Storage temperature range
IPP Tj Tstg TL
Maximum lead temperature for soldering during 10 s
1. For a surge greater than the maximum values, the diode will fail in short-circuit.
Figure 2.
Symbol VBR VCL IRM VRM IPP IR IPP RI/O Cline
Electrical characteristics (definitions)
Parameter Breakdown voltage Clamping voltage Leakage current @ VRM Stand-off voltage Peak pulse current Breakdown current Forward current Series resistanc between input and output Input capacitance per line
I
= = = = = = = = =
VBR VRM
IR IRM IRM IR VRM VBR
V
Table 2.
Symbol VBR IRM Rd Cline
Electrical characteristics (values, Tamb = 25 C)
Test condition From pin1 to pin2, IR = 1 mA (direct) From pin2 to pin1, IR = 1 mA (reverse) VRM = 3 V Square pulse, IPP = 1 A tp = 2.5 s F = 1 MHz, VR = 0 V 650 26 30 Min. 11 5 Typ. 13 V 8 50 nA m pF Max. Unit
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ESDALC5-1BM2, ESDALC5-1BT2
Characteristics
Figure 3.
Relative variation of peak pulse power versus initial junction temperature
Figure 4.
Relative variation of leakage current versus junction temperature (typical values)
1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0
PPP[Tjinitial]/PPP[Tjinitial = 25C]
1000
IR[Tj]/IR[Tj = 25 C]
100
10
Tj(C)
0 25 50 75 100 125 150
1 25 50 75 100
Tj(C)
125
Figure 5.
Peak pulse power versus Figure 6. exponential pulse duration (direct)
10000
Peak pulse power versus exponential pulse duration (reverse)
10000
PPP(W)
PPP(W)
1000
1000
100
100
10
10
1 1 10 100
TP(s)
1000
1 1 10 100
TP(s)
1000
Figure 7.
Clamping voltage versus peak pulse current (typical values, exponential waveform, direct)
Figure 8.
Clamping voltage versus peak pulse current (typical values, exponential waveform, reverse)
100.0
IPP(A)
100.0
IPP(A)
10.0
10.0
1.0
1.0
0.1
VCL(V)
8 10 12 14 16 18 20 22
0.1 6 8 10 12 14
VCL(V)
16
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Characteristics Figure 9. Junction capacitance versus reverse applied voltage (typical values, direct)
ESDALC5-1BM2, ESDALC5-1BT2 Figure 10. Junction capacitance versus reverse applied voltage (typical values, reverse)
50
50
C(pF)
C(pF)
40
40
30
30
20
20
10
10
0 0 1 2 3 4
VLINE(V)
5
0 0 1 2 3 4
VLINE(V)
5
Figure 11. ESD response to IEC 61000-4-2 (+15kV air discharge)
5 V/Div
Figure 12. ESD response to IEC 61000-4-2 (-15kV air discharge)
5 V/Div
C2
C2
100 ns/Div
100 ns/Div
Figure 13. S21 attenuation measurement result
0 -5 - 10 - 15 - 20 - 25 - 30 - 35 - 40 100k 1M 10M 100M
Figure 14. Static characteristic
dB
Direct
Reverse
F(Hz)
1G
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Doc ID 16936 Rev 1
ESDALC5-1BM2, ESDALC5-1BT2
Ordering information scheme
2
Ordering information scheme
Figure 15. Ordering information scheme
ESDA LC
ESD array Low capacitance Breakdown voltage 5 = 5 Volts min Number of lines Directional B = Bi-directional Package M2 = SOD882 T2 = Thin SOD882
5 - 1 B x2
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Package information
ESDALC5-1BM2, ESDALC5-1BT2
3
Package information

Epoxy meets UL94, V0 Lead-free packages
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. Figure 16. SOD882 dimension definitions
D
INDEX AREA (D/2 x E/2)
E
A
A1
b1
INDEX AREA (D/2 x E/2)
b2
L1
OPTIONAL PIN # 1 ID
L2
e
Table 3.
SOD882 dimension values
Dimensions
Ref. Min. A A1 b1 b2 D E e L1 L2 0.45 0.45 0.40 0.00 0.20 0.20
Millimeters Typ. 0.47 Max. 0.50 0.05 0.25 0.25 1.00 0.60 0.65 0.50 0.50 0.55 0.55 0.018 0.018 0.30 0.30 Min. 0.016 0.000 0.008 0.008
Inches Typ. 0.019 Max. 0.020 0.002 0.010 0.010 0.039 0.024 0.026 0.020 0.020 0.022 0.022 0.012 0.012
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ESDALC5-1BM2, ESDALC5-1BT2
Package information
Figure 17. SOD882 footprint in mm (inches)
Figure 18. SOD882 marking
0.55 0.022
0.55 0.022
0.020
0.50
Pin1
G
Pin 2
0.40 0.016
Note: Product marking may be rotated by 90 for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose. Figure 19. SOD882 tape and reel specifications
0.20 0.05
1.10 0.05
8.0 + 0.3 /-0.1
0.66 0.05
0.68 0.05
2.0 0.10
All dimensions in mm
User direction of unreeling
Doc ID 16936 Rev 1
3.5 - 0.05
X X X X X X X
1.75 0.1
Bar indicates Pin 1
2.0 0.05
4.0 0.1
O 1.50 0.10
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Package information Figure 20. SOD882T dimension definitions
D
INDEX AREA (D/2 x E/2)
ESDALC5-1BM2, ESDALC5-1BT2
E
A b1
INDEX AREA (D/2 x E/2)
A1
b2
L1
OPTIONAL PIN # 1 ID
L2
e
Table 4.
SOD882T dimension values
Dimensions
Ref. Min. A A1 b1 b2 D E e L1 L2 0.45 0.45 0.30 0.00 0.20 0.20
Millimeters Typ. Max. 0.40 0.05 0.25 0.25 1.00 0.60 0.65 0.50 0.50 0.55 0.55 0.018 0.018 0.30 0.30 Min. 0.012 0.000 0.008 0.008
Inches Typ. Max. 0.016 0.002 0.010 0.010 0.039 0.024 0.026 0.020 0.020 0.022 0.022 0.012 0.012
Figure 21. SOD882T footprint
Figure 22. SOD882T marking
0.55 0.022
0.55 0.022
0.020
0.50
Pin1
H
Pin 2
0.40 0.016
Note: Product marking may be rotated by 90 for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose.
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Doc ID 16936 Rev 1
ESDALC5-1BM2, ESDALC5-1BT2 Figure 23. SOD882T tape and reel specifications
Package information
0.20 0.05
1.15 0.05
8.0 0.1
0.47 0.05
0.70 0.05
2.0 0.10
All dimensions in mm
User direction of unreeling
Doc ID 16936 Rev 1
3.5 - 0.05
X X X X X X X
1.75 0.1
Bar indicates Pin 1
2.0 0.05
4.0 0.1
O 1.50 0.10
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Recommendation on PCB assembly
ESDALC5-1BM2, ESDALC5-1BT2
4
4.1
Recommendation on PCB assembly
Stencil opening design
1. General recommendation on stencil opening design a) Stencil opening dimensions: L (Length), W (Width), T (Thickness).
Figure 24. Stencil opening dimensions
L
T
W
b)
General design rule Stencil thickness (T) = 75 ~ 125 m W Aspect Ratio = ---- 1.5 T LxW Aspect Area = --------------------------- 0.66 2T ( L + W )
2.
Reference design a) b) c) Stencil opening thickness: 100 m Stencil opening for central exposed pad: Opening to footprint ratio is 50%. Stencil opening for leads: Opening to footprint ratio is 90%.
Figure 25. Recommended stencil window position
Package footprint
Lead footprint on PCB Lead footprint on PCB
Stencil window position
0.39 mm
Stencil window position
0.45 mm 0.05 mm 0.05 mm
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ESDALC5-1BM2, ESDALC5-1BT2
Recommendation on PCB assembly
4.2
Solder paste
1. 2. 3. 4. Halide-free flux qualification ROL0 according to ANSI/J-STD-004. "No clean" solder paste is recommended. Offers a high tack force to resist component movement during high speed. Solder paste with fine particles: powder particle size is 20-45 m.
4.3
Placement
1. 2. 3. 4. Manual positioning is not recommended. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering. Standard tolerance of 0.05 mm is recommended. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools.
5. 6.
4.4
PCB design preference
1. 2. To control the solder paste amount, the closed via is recommended instead of open vias. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away.
Doc ID 16936 Rev 1
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Recommendation on PCB assembly
ESDALC5-1BM2, ESDALC5-1BT2
4.5
Reflow profile
Figure 26. ST ECOPACK(R) recommended soldering reflow profile for PCB mounting
Note:
Minimize air convection currents in the reflow oven to avoid component movement.
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ESDALC5-1BM2, ESDALC5-1BT2
Ordering information
5
Ordering information
Table 5. Ordering information
Marking(1) G H Package SOD882 SOD882T Weight 0.92 mg 0.76 mg Base qty 12000 12000 Delivery mode Tape and reel Tape and reel
Order code ESDALC5-1BM2 ESDALC5-1BT2
1. The marking can be rotated by 90 to differentiate assembly location
6
Revision history
Table 6.
Date 02-Feb-2010
Document revision history
Revision 1 Initial release. Changes
Doc ID 16936 Rev 1
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ESDALC5-1BM2, ESDALC5-1BT2
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